1. Field of the Invention
This invention relates to memory arrangements such as a read only memory (“ROM”), and in particularly to a memory arrangement having reduced power consumption.
2. Description of the Related Art
FIG. 1 illustrates a prior art read-only memory (ROM) 8 having many 1-bit memory cells, corresponding to the memory capacity of the ROM. These 1-bit memory cells are divided into various sections (also called block columns below) of equal size (equal number of 1-bit memory cells), depending on a word length of an output data item of the ROM. In each section, the 1-bit memory cells are arranged in columns and rows. A word line 3 of the ROM runs along the same row in all sections of the ROM. On the other hand, a virtual supply voltage line 1 and a bit line 2 run along a column in only one section of the ROM. This means that the virtual supply voltage lines 1 run parallel to the bit lines 2 along all memory cells which are arranged in a column.
In the case of traditional ROMs, a 1-bit memory cell which represents a logical “0” is usually constructed out of an NMOS transistor having a gate terminal connected to a word line 3, one of the source or drain terminals connected to a virtual supply voltage line 1, and the other terminal being connected to a bit line 2. There are several possibilities for constructing a 1-bit memory cell 4 that represents a logical “1”. For instance, both the source and the drain terminals can be connected to the same bit line 2, or to the same virtual supply voltage line 1, or at least one of the two source and drain terminals hangs in the air, i.e. is connected neither to a bit line 1 nor to a virtual supply voltage line 1.
In the case of a ROM read operation, in which a data item for an address is read, starting from the address, one word line 3 and n (n corresponds to the word width, or number of bits, of the data item to be read) virtual supply voltage lines 1 are specified, and are then activated in the course of the read operation. The address is divided into a row address part and a column address part, the word line 3 being determined by means of the row address part and the virtual supply voltage lines 1 being determined by means of the column address part.
When a 1-bit memory cell 4 which represents a logical “0” is read, the following occurs: Whereas all bit lines 2 are on a first supply voltage potential before the read operation, the virtual supply voltage line 1 corresponding to the address and a bit position in the data item to be read are put or activated onto a second supply voltage potential only in the course of the read operation, and the word line 3 corresponding to the address is activated. In this way the NMOS transistor which represents the logical “0” becomes conducting, so that the bit line which is connected to the NMOS transistor is charged onto the second supply voltage potential. On the other hand, when a 1-bit memory cell 4 which represents a logical “1” is read, the NMOS transistor (if a transistor is present at all) becomes non-conducting, so that the bit line is not charged onto the second supply voltage potential.
For instance, the first supply voltage potential could be VSS and the second supply voltage potential could be VDD, or conversely the first supply voltage potential could be VDD and the second supply voltage potential could be VSS.
In FIG. 1, two sections or block columns 12 are shown. Result bit lines 5 of these two block columns 12 represent the least significant and most significant bits of the data item to be read from the ROM 8. The block columns between these two block columns 12 are only indicated in FIG. 1. Each result bit line 5 is the output of a multiplexer 11, in which case, in the context of a read operation, the bit line 2 corresponding to the address or column address part is switched to the output of the multiplexer 11.
Since, in the case of the ROM 8 according to the prior art, in a column 16 a virtual supply voltage line 1 runs parallel to a bit line 2 over the whole column length, the gap between the virtual supply voltage line 1 and the bit line 2 being extremely small because of the dimensions, which are becoming ever smaller, of the design techniques which are used today, the coupling capacitance or cross-coupling between the virtual supply voltage line 1 and the bit line 2 is great. Because of the coupling capacitance, the bit line 2 is also charged onto the second supply voltage potential if the virtual supply voltage line 1 is charged onto the second supply voltage potential in the course of a read operation. In the case of reading a logical “0”, this is a positive effect, since the bit line 2 is charged onto the second supply voltage potential in the course of an operation to read a logical “0”. On the other hand, in the case of reading a logical “1” it is a counter-productive effect, since the bit line 2 should remain on the first supply voltage potential in the course of an operation to read a logical “1”. Therefore, when reading a logical “1”, it is necessary to wait for a restoration period, until the bit line 2 is again at least near the first supply voltage potential, before the result bit line 5 which corresponds to the bit line 2 is evaluated. Since it is in the nature of the matter that before a read operation it is not known whether a logical “0” or a logical “1” is read, it is always necessary to wait for the restoration period, irrespective of whether a logical “0” or a logical “1” is read. Thus the restoration period decides a clock rate at which the ROM 8 can be read.
In addition to the negative effect on the clock rate of the ROM 8, the coupling capacitance has a negative effect on the power consumption of the ROM 8. Additionally, there is a negative effect on the power consumption by the inherent capacitance of each virtual supply voltage line 1, which must be charged onto the second supply voltage at a read operation. That is, the greater the coupling capacitance and/or the inherent capacitance is, the greater the power consumption that is necessary to charge the corresponding virtual supply voltage lines 1 onto the second supply voltage potential.
In the case of a ROM, in which words with a word width of n bits are stored, in the course of a read operation, n virtual supply voltage lines 1 must be charged onto the second supply voltage potential, and brought back to the first supply voltage potential after the evaluation of the result bit lines 5. Therefore, specifically in the case of ROMs with a large word width, the inherent capacitance and also the coupling capacitance are decisive for the power consumption and maximum clock frequency of the ROM.
Therefore it is desirable to provide a memory arrangement in which the coupling capacitance and inherent capacitance are as small as possible in the case of a read operation.